- 定價93.00元
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8
折優惠：HK$74.4
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DIGITAL SYSTEM DESIGNS AND PRACTICES: USING VERILOG HDL AND FPGAS
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沒有庫存
訂購需時10-14天
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9780470823231 | |
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LIN | |
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全華科技 | |
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2009年1月01日
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460.00 元
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HK$ 437
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詳
細
資
料
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* 叢書系列：大學電子
* 規格：精裝 / 836頁 / 普級 / 單色印刷 / 初版
* 出版地：台灣
大學電子
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薦
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內
容
簡
介
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System-on-a-chip (SoC) has become an essential technique to lower product costs and maximize power efficiency, particularly as the mobility and size requirements of electronics continues to grow. It has therefore become increasingly important for electrical engineers to develop a strong understanding of the key stages of hardware description language (HDL) design flow based on cell-based libraries or field-programmable gate array (FPGA) devices. Honed and revised through years of classroom use, Lin focuses on developing, verifying, and synthesizing designs of practical digital systems using the most widely used hardware description Language: Verilog HDL.
本書特色
1 . Explains how to perform synthesis and verification to achieve optimized synthesis results and compiler times
2 . Offers complete coverage of Verilog syntax Illustrates the entire design and verification flow using an FPGA case study
3 . Presents real-world design examples such as LED and LCD displays, GPIO, UART, timers, and CPUs
4 . Emphasizes design/implementation tradeoff options, with coverage of ASICs and FPGAs
5 . Provides an introduction to design for testability
6 . Gives readers deeper understanding by using problems and review questions in each chapter
7 . Comes with downloadable Verilog HDL source code for most examples in the text
8 . Includes presentation slides of all book figures for student reference
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目
錄
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Chapter 1: Introduction.
Chapter 2: Structural Modeling.
Chapter 3: Dataflow Modeling.
Chapter 4: Behavioral Modeling.
Chapter 5: Tasks, Functions, and UDPs.
Chapter 6: Hierarchical Structural Modeling.
Chapter 7: Advanced Modeling Techniques.
Chapter 8: Combinational Logic Modules.
Chapter 9: Sequential Logic Modules.
Chapter 10: Design Options of Digital Systems.
Chapter 11: System Design Methodology.
Chapter 12: Synthesis.
Chapter 13: Verification.
Chapter 14: Arithmetic Modules.
Chapter 15: Design Examples.
Chapter 16: Design for Testability.
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